1. Field of Invention
This invention relates to computer systems, and more particularly to computer system bus structures used to interconnect system components.
2. Description of Related Art
A typical computer system includes one or more sets of wires (i.e., buses) which serve as shared communication links between system components. The two major advantages of shared buses over direct communication links are versatility and low cost. By defining a standard interconnection scheme for a given bus, new devices may be easily connected to the bus. The cost of the bus is low because it is shared among the number of components connected to the bus.
Each bus has at least one component connected to it which can initiate a transfer of data. Such components are called "bus master" devices. Other devices coupled to the bus and capable only of responding to data transfer requests initiated by bus master devices are called "slave" devices. For example, a typical computer system includes a CPU coupled to a memory system via a bus. The CPU executes instructions stored in the memory system, and initiates transfers of instructions from the memory system as needed. The CPU also transfers data to the memory system for storage as required. The CPU is, by definition, a bus master device. The memory system simply responds to data transfer requests initiated by the CPU and is a slave device. A computer system including multiple CPUs or other components coupled to a common bus and capable of initiating data transfers has multiple bus master devices. In such systems, each bus master device must compete with the other bus master devices for control of the bus when the bus is needed.
A typical computer system bus (i.e., system bus) includes multiple address, data, and control signal lines. Such system buses are typically divided into an address bus including the address signal lines, a data bus including the data signal lines, and a control bus including the control signal lines. Data transfers across the system bus are carried out using bus "transactions". A bus master device (e.g., the CPU) performs a "read" transaction in order to obtain needed data from another system component coupled to the system bus. During the read transaction, the bus master device transmits address signals upon the address bus and control signals indicative of a request for data (i.e., a read transaction) upon the control bus. Upon receiving the address and control signals, the target system component (e.g., the memory system) accesses the requested data. The target component then transmits data signals representing the requested data upon the data bus and control signals which indicate the availability of the data upon the control bus. In many computer systems, the bus master device maintains control of the system bus during the entire period of time between transmission of the address signals and reception of the requested data.
When performing a "write" transaction, the bus master device transmits address signals upon the address bus, data signals representing the data upon the data bus, and control signals indicating a transmission of data (i.e., a write transaction) upon the control bus. Upon receiving the address and control signals, the target system component (e.g., the memory system) stores the data signals. Following simultaneous transmission of address, data, and control signals during a write transaction, the bus master device typically assumes reception of the data by the target component and immediately relinquishes control of the system bus.
In order to make more efficient use of the system bus, several data units (e.g., 8-bit bytes, 16-bit words, etc.) may be transmitted from one system component to another over the bus during a single bus transaction. The data units are typically transmitted one after another in sequence. Such "burst mode" transmission allows more data units to be transmitted over the system bus in a shorter length of time.
Where multiple bus master devices share a common system bus, it is often necessary to limit the amount of time that any one bus master device has control of the system bus. One method of limiting the amount of time a bus master device has control of the system bus is to split read transactions into separate "address" and "data" portions. A bus master device transmits the address and associated control signals during the address portion of a read transaction. Following the address portion, the bus master device relinquishes control of the system bus, allowing other bus master devices to use the system bus while the target component is accessing the requested data. When the target component is ready to transmit the requested data, the target component transmits data signals representing the requested data and associated control signals during the data portion of the read transaction. Such a bus configuration is called a "split transaction" bus.
In a system employing a split transaction bus, each bus master device generates a "tag" value which uniquely identifies the transaction. The tag value is transmitted along with information associated with the transaction (e.g., address or data signals), typically upon signal lines of the control bus. Each system component coupled to the bus typically includes a "transaction queue" used to track outstanding bus transactions. The tag values of outstanding transactions are stored within the transaction queue. The tag value of an outstanding transaction is removed from the transaction queue (i.e., "retired") when the transaction is complete. For write transactions, a system component may retire the associated tag value immediately after the transmission of the associated address, data, and control signals. A bus master device initiating a read transaction may not retire the tag value until the data portion of the read transaction is completed (i.e., until the requested data is received from the target component).
A problem arises when data signals cannot be conveyed upon the data bus at a rate fast enough to satisfy the needs of all bus master devices coupled to the system bus. This often occurs during burst mode data transfers (e.g., cache line fills and frame buffer reads and writes). In such cases, the transaction queues of the bus master devices become full. When a bus master device's transaction queue is full, the bus master device must wait for an outstanding bus transaction to complete (i.e., a tag value to be retired from the transaction queue) before another bus transaction can be initiated. As a result, the address bus experiences periods of nonuse (i.e., is underutilized) while utilization of the data bus is at or near a maximum value.
FIG. 1 is a chart of address and data portions of bus transactions occurring over a split transaction bus versus time. FIG. 1 illustrates the situation where data signals cannot be conveyed upon the data signal lines (i.e., the data bus) of the split transaction bus at a rate fast enough to satisfy the needs of all devices coupled to the split transaction bus. As a result, the devices are not able to initiate as many bus transactions, and the address signal lines (i.e., the address bus) of the split transaction bus experiences periods of nonuse 8 while the data bus is in constant use.
It would be beneficial to have a computer system including a system bus shared by system components wherein during periods of maximum or near-maximum data bus utilization, the underutilized address bus is used to transfer data. During such periods, the desired system bus advantageously exploits the underutilized transmission capability of the address bus in order to increase data transmission efficiency. As a result, the overall performance of the computer system is improved.